IC Substrate Coefficient of Thermal Expansion (CTE) Evaluation: Testing Guide, Methods, and Standard

IC substrate coefficient of thermal expansion (CTE) evaluation is a critical reliability test that measures dimensional stability of package substrates across operating temperature ranges. Accurate CTE characterization of core materials, build-up films, and finished substrates helps semiconductor manufacturers prevent warpage, solder joint fatigue, and delamination failure caused by thermal expansion mismatch between the silicon die, substrate, and printed circuit board.

Technical Overview

The coefficient of thermal expansion (CTE) is one of the most important thermomechanical properties of an IC substrate, defined as the fractional change in dimension per degree of temperature change and typically expressed in ppm/°C. In semiconductor packaging, the IC substrate serves as the mechanical and electrical interposer between the silicon chip and the system circuit board. Because the silicon die exhibits a CTE of approximately 2.6–3.0 ppm/°C while standard FR-4 printed circuit boards range from 14 to 17 ppm/°C, the substrate must be engineered to bridge this mismatch and minimize thermomechanical stress across the entire assembly.

CTE evaluation characterizes both the in-plane expansion (X and Y directions) and the out-of-plane expansion (Z direction) of substrate materials. Organic substrates are strongly anisotropic: common BT (bismaleimide triazine) resin and ABF (Ajinomoto Build-up Film) systems typically show in-plane CTE values of 10–17 ppm/°C below the glass transition temperature, while out-of-plane CTE can reach 30–60 ppm/°C. Two expansion coefficients are distinguished during evaluation: alpha1, measured below the glass transition temperature (Tg), and alpha2, measured above Tg, where the softened resin expands significantly faster. The Tg itself is simultaneously determined from the intersection of the two linear expansion segments in the TMA curve.

Poorly controlled CTE directly causes package-level failures including substrate warpage, solder ball joint fatigue during thermal cycling, interfacial delamination between dielectric and copper layers, and cracking of fragile low-k dielectric layers on advanced silicon devices. As package formats evolve toward larger FC-BGA body sizes, thinner cores, and heterogeneous 2.5D/3D integration, precise CTE evaluation has become an indispensable qualification and incoming-inspection step in the substrate supply chain.

Testing Samples

Bare Laminates and Core Materials

Core materials such as BT resin laminates, low-CTE glass-fabric-reinforced cores, modified epoxy cores, glass cores, and ceramic substrates (for example alumina with a CTE near 6–7 ppm/°C) are tested in coupon form. Samples are cut from production panels at representative locations, dried to remove absorbed moisture, and machined with parallel top and bottom surfaces suitable for the TMA expansion probe.

Build-up Film and Dielectric Materials

Photosensitive build-up dielectric films, including ABF and similar low-dielectric formulations, are evaluated in film tension mode or as laminated stacks. Because these films are typically 15–60 µm thick, multiple layers are often stacked or tested with a dedicated thin-film fixture to obtain reliable displacement resolution.

Finished IC Substrates and Patterned Coupons

Completed substrates with copper redistribution layers, plated through-holes, and solder mask can be evaluated to determine the effective (composite) CTE of the finished construction. Copper patterning, residual stress from plating, and lamination history all influence the apparent expansion behavior, so finished-part testing reflects real-world performance more closely than raw material data alone.

Testing Items

A comprehensive IC substrate CTE evaluation program typically includes the following measurement items:

• In-plane CTE (X and Y directions) below Tg, reported as alpha1
• Out-of-plane CTE (Z direction) below Tg, reported as alpha1
• Out-of-plane CTE above Tg, reported as alpha2
• Glass transition temperature (Tg) determined by the TMA expansion method
• Delta CTE (alpha2 minus alpha1) as an indicator of post-Tg stability
• CTE anisotropy ratio between in-plane and out-of-plane directions
• Effective composite CTE of finished, patterned substrates
• Dimensional change measurements at specific peak temperatures such as 150°C, 200°C, and 260°C to simulate reflow exposure

Testing Methods

Thermomechanical Analysis (TMA)

TMA is the industry-standard technique for IC substrate CTE evaluation, performed in accordance with IPC-TM-650 method 2.4.24, ASTM E831, and ISO 11359-2. A specimen, commonly 3–6 mm square or a strip measuring approximately 6–10 mm in length with a thickness of 0.2–1.5 mm, is placed on a quartz platform beneath a flat-tipped expansion probe applying a low static force of typically 5–20 mN. The furnace heats the specimen at a controlled rate of 5°C/min under a nitrogen purge, while a highly sensitive displacement sensor records dimensional change as a function of temperature.

The test program normally spans from room temperature (or 0°C) to 260°C or higher, covering alpha1 (for example 50–150°C below Tg), the Tg transition region, and alpha2 above Tg. The slope of the linear segment of the expansion curve yields the CTE, and the intersection of the extrapolated alpha1 and alpha2 lines defines Tg. Specimen preparation is critical: faces must be parallel within tight tolerances, moisture is removed by pre-baking (for example 105°C for 2 hours), and edges must be free of fraying or delamination that would distort probe contact.

Dilatometry

Push-rod dilatometry following ASTM E228 is applied to larger or thicker coupons where a longer measurement baseline improves accuracy. A horizontal or vertical dilatometer measures expansion of a rod-shaped specimen, typically 25 mm in length, and is well suited for ceramic substrates, glass cores, and low-expansion engineered materials where sub-ppm/°C resolution is required.

Strain Gauge Method

Foil strain gauges bonded to full-size substrate panels or finished packages measure in-plane effective CTE under controlled thermal chamber conditions. This method captures the behavior of real product geometry, including copper distribution effects and residual stress relaxation, and is frequently used to validate finite element warpage simulation models for large-body FC-BGA and chiplet packages.

Applications

CTE evaluation data supports every stage of the IC substrate and semiconductor packaging lifecycle:

• Material qualification and supplier comparison for core laminates, build-up films, and adhesive systems against specifications such as IPC-4101 and IPC-4103
• Substrate design optimization, including selecting low-CTE cores and glass cores to match silicon and reduce die-underfill stress
• Warpage prediction and finite element simulation inputs for flip-chip, FC-BGA, CSP, and SiP packages
• Solder joint reliability assessment during temperature cycling (for example -55°C to 125°C per JEDEC JESD22-A104) and multiple reflow exposure at 260°C peak
• Advanced packaging development for 2.5D interposers, 3D stacked die, high-density fan-out, and chiplet integration where CTE mismatch management is the dominant design constraint
• Incoming quality control and statistical process monitoring at substrate fabrication facilities
• Failure analysis, where anomalous alpha2 or unexpectedly low Tg indicates incomplete resin cure, moisture uptake, or material degradation

FAQ

What CTE value is considered good for an IC substrate?

For flip-chip and FC-BGA applications, an in-plane CTE of approximately 8–14 ppm/°C is generally targeted, which sits between the CTE of silicon (about 3 ppm/°C) and the PCB (about 15–17 ppm/°C). Memory and wire-bond CSP substrates often tolerate slightly higher values, while silicon-matched designs such as 2.5D interposer carriers demand low-CTE glass or ceramic cores in the range of 3–9 ppm/°C.

What is the difference between alpha1 and alpha2?

Alpha1 is the CTE below the glass transition temperature and represents normal device operating conditions. Alpha2 is the CTE above Tg, where the polymer matrix softens and expansion increases sharply, often two to four times alpha1. A small delta between alpha1 and alpha2 indicates better dimensional stability through processing temperature excursions such as reflow.

Which standards govern IC substrate CTE testing?

The primary standards are IPC-TM-650 method 2.4.24 (time for TMA measurement of CTE and Tg for PCB and substrate materials), ASTM E831 for linear expansion by TMA, ISO 11359-2, and ASTM E228 for dilatometry. Package-level reliability expectations reference JEDEC thermal cycling and warpage test methods.

Why must samples be dried before CTE measurement?

Organic substrates absorb ambient moisture, which produces a moisture-induced expansion signal that overlaps with true thermal expansion and depresses the measured Tg. Pre-baking at approximately 105°C for 2 hours, or per the applicable material specification, ensures the reported CTE reflects intrinsic material behavior.

How does CTE mismatch cause solder joint failure?

During thermal cycling, differential expansion between die, substrate, and board shears the solder joints with every cycle. Repeated plastic deformation accumulates fatigue damage, initiates cracks at the intermetallic interface, and eventually results in electrical opens. Matching substrate CTE to the die and board stack reduces shear strain per cycle and extends joint fatigue life.